High-level synthesis (HLS) is a powerful tool for designing digital circuits. It enables designers to quickly and efficiently create complex circuits from high-level descriptions, such as C/C++ or SystemC. However, the performance of these circuits can be unpredictable and difficult to verify. To address this issue, researchers at ETH Zurich have developed a formal verification technique for enhancing the performance of HLS-generated circuits.
The technique, called “Formal Verification for Enhancing the Performance of High-Level Synthesis-Generated Circuits” (FVEC), is based on a combination of formal verification and high-level synthesis. It uses a formal verification tool to analyze the circuit’s behavior and identify potential performance issues. The tool then generates a set of constraints that can be used to improve the circuit’s performance.
The FVEC technique has been tested on several real-world circuits, including a processor core and a memory controller. The results show that FVEC can significantly improve the performance of HLS-generated circuits. For example, in the case of the processor core, the FVEC technique was able to reduce the power consumption by up to 25%.
In addition to improving the performance of HLS-generated circuits, the FVEC technique also provides additional benefits. For instance, it can help designers identify potential design flaws before they are implemented in hardware. This can help reduce development time and cost, as well as improve the reliability of the final product.
Overall, the FVEC technique developed by ETH Zurich is an important step forward in the field of high-level synthesis. It provides designers with a powerful tool for improving the performance of their HLS-generated circuits, while also helping to reduce development time and cost. As such, it is likely to become an essential part of the design process for many digital circuits in the future.
Source: Plato Data Intelligence: PlatoAiStream