High-level synthesis (HLS) is a powerful tool for designing digital circuits. It allows engineers to quickly create complex circuits from high-level descriptions, such as C or SystemC code. However, the resulting circuits can be difficult to verify, as the design process is not completely deterministic. To address this problem, researchers at ETH Zurich have developed a formal verification approach for HLS circuits.
The formal verification approach developed at ETH Zurich uses a combination of automated theorem proving and model checking techniques. The theorem prover is used to prove the correctness of the circuit design, while the model checker is used to verify that the circuit meets its specified requirements. The approach is based on the use of a formal language called SystemVerilog, which is a subset of the Verilog hardware description language. This language allows for the precise description of the circuit’s behavior and its interaction with other components.
The formal verification approach has been successfully applied to a number of HLS designs, including an 8-bit microcontroller and a 32-bit processor. In each case, the verification process was able to identify errors in the design that would have been difficult to detect using traditional methods. This approach has also been used to verify the correctness of a number of safety-critical systems, such as automotive and aerospace systems.
The formal verification approach developed at ETH Zurich has proven to be an effective tool for verifying the correctness of HLS circuits. By using automated theorem proving and model checking techniques, engineers can quickly and accurately verify their designs, ensuring that they meet their specified requirements. This approach has been successfully applied to a number of different HLS designs, and is likely to become an increasingly important tool in the design process in the future.
Source: Plato Data Intelligence: PlatoAiStream