{"id":2421188,"date":"2023-03-05T11:57:50","date_gmt":"2023-03-05T16:57:50","guid":{"rendered":"https:\/\/xlera8.com\/formal-verification-of-hls-produced-circuits-at-eth-zurich\/"},"modified":"2023-03-20T16:54:46","modified_gmt":"2023-03-20T20:54:46","slug":"formal-verification-of-hls-produced-circuits-at-eth-zurich","status":"publish","type":"platowire","link":"https:\/\/platoai.gbaglobal.org\/platowire\/formal-verification-of-hls-produced-circuits-at-eth-zurich\/","title":{"rendered":"Formal Verification of HLS-Produced Circuits at ETH Zurich."},"content":{"rendered":"<p>High-level synthesis (HLS) is a powerful tool used in the development of digital circuits. It enables designers to quickly and efficiently create complex digital systems from a high-level description. However, the quality of the resulting circuit is highly dependent on the quality of the HLS-produced code. To ensure that the circuits produced by HLS are of high quality, formal verification techniques are being developed at ETH Zurich. <\/p>\n<p>Formal verification is a process of mathematically proving that a given system meets its desired specifications. It is used to ensure that the system behaves as expected and does not contain any errors. At ETH Zurich, formal verification techniques are being developed to verify the correctness of HLS-produced circuits. This involves verifying that the circuit meets its desired functionality and is free from any errors or bugs. <\/p>\n<p>The formal verification process at ETH Zurich consists of two main steps. First, the HLS-produced code is analyzed to identify any potential errors or bugs. This is done by using static analysis techniques such as symbolic execution and model checking. These techniques are used to detect any inconsistencies in the code that could lead to incorrect behavior. <\/p>\n<p>Once any potential errors have been identified, the second step of the process is to formally verify that the circuit meets its desired functionality. This is done by using a combination of theorem proving and model checking techniques. Theorem proving is used to mathematically prove that the circuit meets its desired functionality while model checking is used to verify that any potential errors have been eliminated. <\/p>\n<p>The formal verification techniques being developed at ETH Zurich are an important tool for ensuring that HLS-produced circuits are of high quality. By using these techniques, designers can be confident that their circuits will behave as expected and will be free from any errors or bugs. This will enable them to develop more reliable and efficient digital systems.<\/p>\n<p>Source: Plato Data Intelligence: <a rel=\"noopener\" target=\"_blank\" href=\"https:\/\/platoaistream.com\">PlatoAiStream<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>High-level synthesis (HLS) is a powerful tool used in the development of digital circuits. It enables designers to quickly and efficiently create complex digital systems from a high-level description. However, the quality of the resulting circuit is highly dependent on the quality of the HLS-produced code. To ensure that the circuits produced by HLS are [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":2527035,"menu_order":0,"template":"","format":"standard","meta":[],"aiwire-tag":[11,132,1311,10360,18,20,21,790,23,368,13114,572,140,15957,29,219,5476,8432,19329,2403,144,729,320,4217,3214,227,731,2793,1844,7938,5952,2920,156,157,867,868,19577,3040,1193,40,532,2067,347,41,235,376,10097,3044,19522,5320,2195,743,50,6640,19380,10635,1221,51,4157,1024,55,166,13225,19524,3148,19525,56,5379,603,475,57,9781,2817,60,61,62,692,2090,176,19561,7022,1063,69,75,78,761,79,5,10,7,8,82,624,625,299,2613,1087,2505,89,92,493,1283,7143,12777,19555,778,710,103,19580,7509,781,640,5020,108,109,110,206,207,111,557,115,429,430,278,19364,5303,17730,9,123,124,6,19532],"aiwire":[19097],"_links":{"self":[{"href":"https:\/\/platoai.gbaglobal.org\/wp-json\/wp\/v2\/platowire\/2421188"}],"collection":[{"href":"https:\/\/platoai.gbaglobal.org\/wp-json\/wp\/v2\/platowire"}],"about":[{"href":"https:\/\/platoai.gbaglobal.org\/wp-json\/wp\/v2\/types\/platowire"}],"author":[{"embeddable":true,"href":"https:\/\/platoai.gbaglobal.org\/wp-json\/wp\/v2\/users\/2"}],"version-history":[{"count":1,"href":"https:\/\/platoai.gbaglobal.org\/wp-json\/wp\/v2\/platowire\/2421188\/revisions"}],"predecessor-version":[{"id":2519561,"href":"https:\/\/platoai.gbaglobal.org\/wp-json\/wp\/v2\/platowire\/2421188\/revisions\/2519561"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/platoai.gbaglobal.org\/wp-json\/wp\/v2\/media\/2527035"}],"wp:attachment":[{"href":"https:\/\/platoai.gbaglobal.org\/wp-json\/wp\/v2\/media?parent=2421188"}],"wp:term":[{"taxonomy":"aiwire-tag","embeddable":true,"href":"https:\/\/platoai.gbaglobal.org\/wp-json\/wp\/v2\/aiwire-tag?post=2421188"},{"taxonomy":"aiwire","embeddable":true,"href":"https:\/\/platoai.gbaglobal.org\/wp-json\/wp\/v2\/aiwire?post=2421188"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}